The Controller Area Network (CAN) is a serial communications protocol that can efficiently support distributed real time control with a very high level of security. CAN applications can range from high speed networks to low cost multiplex wiring. Recently, it has been suggested that the ever increasing bandwidth requirements in automotive networks may impede the use of CAN due to its bit rate limitation of 1 Mbit/s. As a result, a relatively new frame format known as ‘CAN with Flexible Date-Rate’ (CAN FD) has been proposed. CAN FD is used to complement CAN in applications that require higher data-rates.
The general operation of CAN FD systems is documented in the art, however, for completeness, a brief summary of a specific operation will be provided here. It is known that both CAN and CAN FD systems feature an automatic arbitration-free transmission. Thus, a CAN message that is transmitted with the highest priority will succeed, and a node transmitting a lower priority message will wait for the highest priority message to be transmitted. This is achieved in a CAN system by transmitting data via a bus through a binary model of ‘dominant’ bits and ‘recessive’ bits, where dominant is logic ‘0’ and recessive is logic T. If a recessive bit is being transmitted while a dominant bit is sent, the dominant bit will be displayed. A dominant bit is achieved by activating a switch, while a recessive bit is simply not asserted on the bus.
In the case of a dominant to recessive transition, the switch is simply disabled, thereby allowing the voltage across the bus to passively transition back to logic ‘1’. During arbitration, each transmitting node monitors the CAN bus state and compares a received bit with the transmitted bit. If a dominant bit is received when a recessive bit was transmitted, the node loses arbitration and stops transmitting. Arbitration is performed during the transmission of the identifier field. Each node in the CAN system starts to transmit at the same time by sending an identifier (ID) with dominant as binary ‘0’, starting from the highest bit. As soon as a node's ID is a larger number (lower priority) they will transmit ‘1’ (recessive) and see ‘0’ (dominant), causing them to lose arbitration and stop transmitting. At the end of ID transmission, all nodes bar one node will have lost arbitration and have stopped transmitting, thereby leaving the node with the highest priority message to transmit.
FIG. 1 illustrates a simplified block diagram of a standard format CAN FD frame 100. The CAN FD frame 100 comprises an arbitration field 102, a control field 104 and a data field 106. The CAN FD frame 100 consists of the same elements as a CAN frame, the primary difference being that in the CAN FD frame 100, the Data Field 106 and cyclic redundancy code (CRC) field (not shown) may be longer (and transmitted at a higher speed). A further difference between normal CAN frames and CAN FD frames is at the reserved bit 108, located immediately after the end of the arbitration field 102. In CAN FD frame 100, this reserved bit 108 is transmitted as a ‘recessive’ level and is renamed ‘Extended Data Length (EDL)’. In standard format CAN FD frame 100 with an 11-bit identifier and extended format CAN FD frames with 29-bit identifiers (not shown), the EDL bit 108 is always followed by the ‘dominant’ bit r0 112, which is reserved for future expansion of the protocol.
The Control Field 104 of the CAN FD frame 100 contains two additional bits, namely Bit Rate Switch (BRS) 114 and Error State Indicator (ESI) 116. BRS 114 determines whether the bit rate is switched inside the frame. If it is transmitted ‘recessive’, the bit rate is switched from the standard bit rate 118 to the optional high bit-rate 120. If BRS 114 is transmitted ‘dominant’, the bit rate is not switched. Thus, the first part of the CAN FD frame 100 (until the BRS bit 114), is transmitted with the same bit-rate as a normal CAN frame, and the bit rate is switched if the BRS bit 114 is ‘recessive’. CAN FD frame 100 has the option to switch from a standard bit rate 118 to a high bit rate 120 during the transmission of the data field 106. Therefore, data intensive applications can be fully supported by the CAN FD protocol.
FIG. 2 illustrates a physical bit electrical representation (according to IS011898 part 2 and part 5) 201 during a data field, such as data field 106 of FIG. 1, for a prior art CAN FD system under normal load. FIG. 2 further illustrates an expanded physical bit electrical representation for a prior art CAN FD system under a high bus capacitance load 220. In physical bit electrical representation 201, the transmitted signal 203 comprises a recessive level defined by a logic ‘1’ 205 and a dominant level defined by a logic ‘0’ 207. The received signal 209 thus incurs a transmission delay between the respective transmitted and the received recessive level, and similarly a transmission delay between the transmitted dominant level 207, and the received dominant level. These respective transmission delays are illustrated as CAN bus levels 211 and 213. The transition times on the CAN FD bus levels 211, 213 effectively limit the maximum baud rate of the CAN system. In this case, there is an active drive transition between CAN bus level 211 and a passive transition between CAN bus levels 213. This is because in current CAN systems, the dominant transition (logic ‘0’) is actively driven, whereas the recessive transition (logic ‘1’) is simply not asserted on the bus by de-activating any active elements that allow the bus to transition passively back to its recessive state (logic ‘1’).
Thus, with regard to the recessive-to-dominant level transition in a CAN FD system, the expanded physical bit electrical representation 220 is essentially the same as 201. However, in the case of known CAN FD systems operating under high bus capacitance load 220, the transition time 222 from dominant-to-recessive level on the CAN bus has been increased due to the increased signal delays present in the CAN FD system. Previously, this increased transition time was not a problem due to the lower data rates being employed within the data field. However, now that CAN FD has the option of utilising an increased data rate during the data field, increased transition times from the dominant to recessive levels have the effect of limiting the maximum baud rate that can be used in the system, and thereby the data rate that can be utilised.
Referring now to FIG. 3, a known CAN FD transceiver circuit 300 is shown comprising, main transceiver circuit 302, parasitic load capacitances and load resistances 304, a CAN Protocol module (located in a main computer unit (MCU)) 306, differential receiver 308, pre-driver 310 and transceiver circuit output driver stages 312, 314. CANH 316 and CANL 318 are differential output signals on the CAN bus 320. CAN transceivers use open-drain transceiver circuit output driver stages 312, 314, where one of the output stages 312 is connected to the supply voltage, and the other open-drain output stage 314 is connected to ground. CAN protocol module 306 transmits a signal to pre-driver 310 that is operable to drive open-drain transceiver circuit output stages 312, 314. Internal resistor network 322 is generally connected to approximately half the supply voltage to create a differential output bus signal at CANH 316 and CANL 318.
If the CAN protocol module 306 determines that it needs to transmit a dominant bit on the CAN bus 320, it instructs the pre driver 310 to enable both open drain output stages 312, 314 so that they conduct, thereby producing voltage levels of typically 3.5V at CANH 316 and typically 1.5V at CANL 318. The resulting differential output voltage constitutes a dominant bit and, therefore, logic low (dominant ‘0’). If the CAN protocol module 306 determines that it needs to transmit a recessive bit on the CAN bus 320, it instructs the pre driver 310 to disable both open drain output stages 312, 314 so that they become high impedance and, therefore, only the Vcc/2 potential is applied via the pull-up resistors 322 to both outputs CANH 316 and CANL 318, which represents logic high (recessive ‘1’). The logic high phase (recessive ‘1’) is not actively driven as in the dominant phase. Therefore, the transition time from dominant to recessive is dependent on the system passively transitioning from logic ‘0’ to logic ‘1’ (e.g. back to Vcc/2). The passive transition from the dominant phase to the recessive phase may increase overall transition time within the CAN bus, leading to a reduction of the maximum data rate that can be utilised during a CAN FD high bit-rate phase.